Clocking at the physical interface of a transmitter or receiver typically controls the speed at which data is transmitted/received on the physical connection. To eliminate transmission jitter resulting from the transmission of data, a jitter buffer often is needed at the receiver. The arrival rate and the departure rate from the jitter buffer typically are controlled, respectively, by the transmitter clock and the receiver clock. Ideally, the same amount of data is transmitted or forwarded at every point in the connection within any given time window when the transmitter clock and reference clock are synchronized. If the physical interfaces along a connection are not synchronized (i.e., not driven by a clocking signal of a substantially similar or equal frequency), data can be lost due to buffer overflow or underflow, resulting in periodic line errors. To keep a stable buffer level, frequency offsets between the transmitter and receiver often are eliminated or reduced either through driving the transmitter clock and receiver clock from a common global clock, or slaving the receiver clock to a transmitter clock by means of a phase-locked loop (PLL) which derives its reference clock signal from clock information provided by the transmitter clock.
One technique commonly implemented in packet-switched networks includes the synchronization of the transmitter clock and the receiver clock using timestamps (see, e.g., R. C. Lau and P. E. Fleischer, “Synchronous Techniques for Timing Recovery in BISDN,” Proc. IEEE GLOBECOM, 1992, pp. 814–820). The transmitter sends a series of explicit time references as timestamps in a sequence of packets and the timestamps are used by the receiver to synchronize its clock to that of the transmitter. Since no common network clock is used, the receiver relies on locking its clock to the arrival of the timestamps. This technique is analogous to the common method of periodic insertion of synchronizing patterns into a bit stream at the transmitter, whereby the receiver is adapted to detect these synchronizing patterns and use them to generate a reference clock signal for a PLL at the receiver.
Techniques have been developed for clock synchronization using a linear modeling of the error between the transmitter clock and the receiver clock. Using a linear regression analysis, the frequency offset between the transmitter clock and a receiver clock for a given time period or time instance is estimated or predicted and the receiver clock then is adjusted by this estimated error.
However, a major disadvantage in the use of the linear regression analysis as an estimation technique (as described above) is that a relatively large number of time series values is needed to accurately estimate the model coefficients at the end of each period. The storage capacity for storing a large number of time series and the associated calculations could be prohibitive.
One clock synchronization technique based on a least-squares linear regression analysis is disclosed in a paper by R. Noro, M. Hamdi, and J. P. Hubaux, “Circuit Emulation over IP Networks,” IFIP 6th Inter. Workshop on Protocols for High-Speed Networks, Salem, Mass., August 1999, pp. 187–201. This least-squares linear regression analysis-based clock synchronization technique observes and processes a relatively large sequence of consecutive clock samples (i.e., timestamps) to generate accurate timing signals. Although this technique and others based on least-squares linear regression analysis generally perform considerably more efficiently than conventional second-order PLLs, these techniques have the drawback of requiring large number of clock samples (thus, a large storage requirement) in order to generate accurate timing signals.
In view of the foregoing, it would be desirable to provide a technique for synchronizing a receiver clock with a transmitter clock that overcomes the above-describe inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for timestamp-based clock synchronization between a transmitter and a receiver in a packet-switched network in an efficient and cost-effective manner.